1. Field of the Invention
The present invention relates to element-to-element interconnection in a semiconductor device and more particularly, to connection between an impurity diffusion layer of a transistor and another element in a semiconductor device.
2. Description of the Related Art
In constructing a semiconductor device, it is often necessary to connect an impurity diffusion layer of a transistor constituting one element of the semiconductor device to a different element. For example, when the different element is a gate electrode of the transistor, the conventional connection is such that a polycrystalline silicon layer constituting the gate electrode is connected directly to the impurity diffusion layer of the transistor or the polycrystalline silicon layer constituting the gate electrode is connected to an overlying metal wiring line and the metal wiring line is connected to the impurity diffusion layer of the transistor. When the former method is used, a gate oxide film formed at a portion of the surface of a semiconductor substrate where the impurity diffusion layer of the transistor is to be formed is removed by wet-etching using a resist film as a mask to form an opening and thereafter, the polycrystalline silicon layer constituting the gate electrode is extended up to the opening. In this method, however, in a step for removal of a resist film following the partial removal of the gate oxide film by using the resist film, the quality of the gate oxide film may possibly be deteriorated and reliability of the semiconductor device may be degraded. The former method may be applied to an SRAM with a configuration disclosed in, for example, JP-A-3-234062.
The latter method as applied to an EEPROM will be described with reference to FIGS. 11 to 14.
Some of non-volatile semiconductor memory devices having memory cell transistors with floating gate such as EEPROM's have transistors for word line select adapted to select on/off of individual word lines. FIG. 11 shows an equivalent circuit of an memory cell array of this type of non-volatile semiconductor memory device. In this memory cell array, eight memory cell transistors 12 each having a floating gate 11 to store data are connected to one word line 13 or a control gate.
Each of the memory cell transistors 12 has a drain connected to a bit line 15 through a select transistor 14 and a source connected to a common source line 16. A word line 13 is connected to a select line 18 through a transistor 17 for word line select and a gate electrode of the word line select transistor 17 and gate electrodes of the select transistors 14 are connected to a select gate line 19.
In this memory cell array, in order to access one of the memory cell transistors 12, a word line 13 connected to a particular word line select transistor 17 is first selected by selecting a select gate line 19 and the discrimination between, for example, a memory cell transistor 12a and a memory cell transistor 12b which are connected to the same word line 13 is effected by selecting a bit line 15.
Although the memory transistor 12a and a memory transistor 12c, for example, are connected to the same bit line 15, only one select gate line 19 is selected and hence only a select transistor 14 paired with, for example, the memory transistor 12a is rendered conductive but a select transistor 14 paired with the memory transistor 12c is not rendered conductive, thus preventing the memory transistor 12c from being accessed.
FIGS. 12 and 13 show a structure of the memory cell array shown in FIG. 11. FIG. 12 is a sectional view taken along line (XII--XII of FIG. 13) which extends from a portion where the select line 18 is connected to the drain of the word line select transistor 17 along the word line 13, while crossing the select gate line 19. In this example, the element isolation regions are defined by silicon oxide films 22 selectively formed in the surface of a silicon substrate 21, and a silicon oxide film 23 serving as a gate insulating film of the word line select transistor 17 and a silicon oxide film 29 serving as a tunnel insulating film of the memory cell transistor 12 are formed on the surface of element active regions each surrounded by the silicon oxide films 22.
The floating gate 11 and a lower layer of the select gate line 19 are formed by a first layer of polycrystalline silicon film 24 on the silicon substrate 21 and a capacitive coupling insulating film of the memory cell transistor 12 is formed by an ONO film 25 covering the floating gate 11. Then, the word line 13 and an upper layer of the select gate line 19 are formed by a second layer of polycrystalline silicon film 26 on the silicon substrate 21.
In the element active regions, impurity diffusion layers 27a and 27b serving as a source and a drain of the word line select transistor 17 and impurity diffusion layers (not shown) serving as sources and drains of the memory transistor 12 and select transistor 14 are formed on both sides of the polycrystalline silicon films 24 and 26. The word line 13 and select gate line 19 are covered with an inter-layer insulating film 28 and contact holes 31 to 33 reaching the word line 13 and the impurity diffusion layers 27a and 27b are formed in the inter-layer insulating film 28.
Then, the wiring line 35 extending between the contact holes 31 and 32 to connect the word line 13 and the impurity diffusion layer 27a, the select line 18 connected to the impurity diffusion layer 27b through the contact hole 33, the bit line 15 and the source line 16 are formed of metal films 34. In FIG. 13, 121 indicates a region at which the first layer of polycrystalline silicon film 24 is to be removed through the first etching and 122 indicates a region at which the ONO film 25 is to be unremoved.
In the above example, however, the impurity diffusion layer 27a serving as the source of the word line select transistor 17 and the word line 13 are connected together by the wiring line 35 formed of the metal film 34 and therefore, it is required to form the contact holes 32 and 31 reaching the impurity diffusion layer 27a and the word line 13, respectively, and to connect them by the wiring line 35. Accordingly, as is clear from FIGS. 12 and 13, an area necessary for connection of one of the impurity diffusion layers 27a of the word line select transistor 17 to the word line 13 is increased, making it difficult to provide a minute non-volatile semiconductor memory device.
Further, when forming the contact holes 31 to 33, a method is generally employed in which the inter-layer insulating film 28 is dry-etched using a patterned resist 36 as a mask. However, as the contact hole 31 reaches the word line 13, the word line 13 in a floating state is exposed to charged particles 37 used for the dry-etching so that the charged particles 37 are accumulated on the word line 13.
As a result, a potential difference takes place between the word line 13 and the silicon substrate 21 so that a voltage is applied to the silicon oxide film 29 serving as the tunnel insulating film in the memory cell transistor 12, thus deteriorating the silicon oxide film 29. Accordingly, the aforementioned prior art has difficulties in providing a highly reliable non-volatile semiconductor memory device.